The invention relates to integrated circuits, such as electronic memory devices, microprocessors, signal processors and integrated logic devices.
Although a DRAM requires continuous refreshing of stored information, speed and information density, combined with a relatively low cost, have put the DRAM to a pivotal position in the field of information technology. Almost every type of computer system takes advantage of this economic and fast data storage technology. In order to store a plurality of data, it is known to those skilled in the art to arrange a plurality of memory cells in a matrix. Every single memory cell out of the matrix may be addressed by using a column address and a row address. It is possible to write and read data to specific addresses in the matrix.
Read and write commands as well as data transport is synchronized by using a clock signal. The clock signal may be generated on the same semiconductor die including the memory cells. As an alternative, the clock signal may be generated by a separate device such as a memory controller, which is coupled with the DRAM and which may be part of a computer system including the DRAM.
Command and data signals traveling on the semiconductor die are subject to unavoidable delays. Therefore, output signals which are generated by the integrated circuit from respective input signals may be out of phase, i.e. not synchronized to the external clock signal.
For these and other reasons, there is a need for the present invention.